FIG. 1 shows a simple circuit layout 100, or equivalently the mask patterns for a circuit. The circuit has four polysilicon gate MOS transistors T1, T2, T3 and T4. Although not shown in FIG. 1, the diffusion regions for transistors T1 and T3 are of a first conductivity type (e.g., N) and the diffusion regions for the other two transistors T2 and T4 are of the opposite conductivity type (P). For instance, if the substrate of the device is a P-type substrate, the right half of the circuit is located in an N-well, and the circuit shown consists of two CMOS inverters connected tail to nose (or cross connected). The mask layers shown are:
a polysilicon (Poly1) mask 102; PA1 an interconnect metal (TiN/Ti) mask 104; PA1 a diffusion mask 106, which actually consists of two masks, one for N-channel transistors and one for P-channel transistors, plus a well mask that is not shown in FIG. 1 at all; PA1 a metal to diffusion contact mask 108 for defining metal layer to diffusion connections; and PA1 a metal to polysilicon contact mask 110 for defining metal layer to polysilicon connections.
For convenience, the two metal regions in the circuit are labeled as regions 112 and 114. Also, the polysilicon layer is herein called Poly1, since in many circuits a second polysilicon layer called Poly2 may also be used.
Referring to FIGS. 1, 2 and 3 method 120 illustrates a conventional semiconductor process for manufacturing the circuit. After performing the normal wafer preparation steps (including well formation and field oxide formation), the gate oxide is deposited along with the polysilicon and cap oxide (or nitride) layers that form the polysilicon gate stack (step 122). Then the Polyl mask is applied and the cap, polysilicon and gate oxide regions are etched using conventional etching techniques to form the polysilicon transistor gate structures (step 124). Then oxide (or nitride) spacers are formed on the sides of the transistor gate structures, the source/drain regions are masked and the source/drain dopants are deposited (or implanted) to form source and drain regions (step 126). In CMOS circuits, two sets of diffusion masks and doping steps are required.
Next, an interlayer dielectric layer is deposited, and contact regions are masked and etched to form contact holes through the interlayer dielectric. These contacts are used for forming metal to diffusion and metal to polysilicon connections.
Then a metal layer such as a layer of TiN (titanium nitride) or Ti or a sandwich of the two is deposited and patterned using the metal layer mask (step 128). The particular etching method used is a potential problem that is discussed in more detail below. The metal layer etching step may create the stringers that are the subject of the present invention. Finally, the remainder of the circuit is formed using downstream processing steps which are not directly relevant to the present discussion.
Referring to FIGS. 1 and 2, the problem addressed by the present invention concerns etching the metal interconnect layer located above the polysilicon transistor gate material layers. In one embodiment, the metal interconnect layer is TiN (titanium nitride), Ti (titanium), or a sandwich of the two, and is separated from the transistor gate stack and diffusion regions by a fairly thin interlayer dielectric layer. In many semiconductor circuits the interlayer dielectric deposited after forming the transistor gate stack is thin and the partially manufactured circuit is not planarized before the metal interconnect layer is deposited and patterned.
There are generally three conventional methods of etching used to pattern the metal layer: isotropic plasma etch, anisotropic plasma etch, and wet etch. The anisotropic etch is highly directional and therefore causes less undercutting, but also tends to leave stringers along the sides of vertical surfaces, such as the sides of polysilicon gate structures. In particular, if metal stringers 118 are left along the side edges 116 of the polysilicon stack structures, those stringers may cause the two metal regions 112 and 114 to be electrically connected, causing the circuit to fail.
The isotropic plasma etch and wet etch methods leave less stringers and in fact could be used to effectively eliminate the metal stringer problem. However, the isotropic plasma etch and wet etch provide much worse control over the "critical dimensions" (CD) of the circuit being manufactured due to undercutting. Therefore, anisotropic plasma etching is highly preferred, so long as the metal stringer problem can be eliminated.
The other conventional approach to eliminating the metal stringer problem, while still using anisotropic plasma etching for metal layer patterning is to planarize the partially formed circuit after forming the polysilicon gate structure but before depositing the metal layer. However, planarizing the circuit is expensive, and causes other problems not relevant here.
It is therefore an object of the present invention to provide a semiconductor manufacturing process that eliminates the interconnect metal layer stringer problem, without requiring circuit planarization before metal layer formation, and while enabling anisotropic plasma etching to be used for metal layer patterning.